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Approximately one year ago, Samsung confirmed the world’s first use of AI to design a mobile processor chip. Since then, AI-driven design has been adopted across the industry at a phenomenal pace, accelerating silicon innovations to market in automotive, high-performance computing, consumer electronics, and other applications. Will this pace of innovation ultimately lead to self-designed silicon? In this sequel to the Day-1 Keynote – Enter the Era of Autonomous Design: Personalizing Chips for 1,000X More Powerful AI Compute, we will be looking at real-world examples of using AI to design chips, and reporting on the industry’s path to autonomous design.

Chip Design
Novel AI Hardware
Hardware Engineering
Industry & Investment

Author:

Stelios Diamantidis

Senior Director & Head of Autonomous Design Solutions
Synopsys

Stelios heads Synopsys' AI Solutions team in the Office of the President, where he researches and applies innovative machine-learning technology to address systemic complexity in the design and manufacturing of integrated computational systems. In 2020, Stelios launched DSO.ai™, the world’s first autonomous AI application for chip design. He has more than 20 years of experience in chip design and EDA software and has founded two companies in this space. Stelios holds an M.S. Electrical Engineering from Stanford University, California.

 

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Stelios Diamantidis

Senior Director & Head of Autonomous Design Solutions
Synopsys

Stelios heads Synopsys' AI Solutions team in the Office of the President, where he researches and applies innovative machine-learning technology to address systemic complexity in the design and manufacturing of integrated computational systems. In 2020, Stelios launched DSO.ai™, the world’s first autonomous AI application for chip design. He has more than 20 years of experience in chip design and EDA software and has founded two companies in this space. Stelios holds an M.S. Electrical Engineering from Stanford University, California.

 

Edge AI
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Software Engineering
Systems Engineering

Author:

Girish Venkataramani

Senior Director, ML Accelerators
Cruise
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Girish Venkataramani

Senior Director, ML Accelerators
Cruise

Author:

Ravi Narayanaswami

Principal MLA Architect
Cruise
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Ravi Narayanaswami

Principal MLA Architect
Cruise

Author:

Prasun Raha

Head of HW Platform Architecture
Rivian
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Prasun Raha

Head of HW Platform Architecture
Rivian

Author:

Nikunj Kotecha

Solutions Architect
BrainChip

Nikunj Kotecha is a Machine Learning Solutions Architect at BrainChip Inc. Currently, he works on developing and optimizing Machine Learning algorithms for the AkidaTM neuromorphic hardware. He also demonstrating capabilities of AkidaTM to client and supports with their neuromorphic solutions for AkidaTM. He has a Master of Science in Computer Science, where he specialized in concepts of Artificial intelligence with Deep Learning algorithms. At the time, he was a part of the Machine Learning lab and has published technical papers, supported research into different avenues of AI. He published research on Cross-Modal Fusion with Transformer architecture for Sign Language translation during the completion of his Masters. He has also worked at Oracle, where he build and integrated Machine Learning solutions to provide operational benefits of using Oracle Clinical Trial software.

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Nikunj Kotecha

Solutions Architect
BrainChip

Nikunj Kotecha is a Machine Learning Solutions Architect at BrainChip Inc. Currently, he works on developing and optimizing Machine Learning algorithms for the AkidaTM neuromorphic hardware. He also demonstrating capabilities of AkidaTM to client and supports with their neuromorphic solutions for AkidaTM. He has a Master of Science in Computer Science, where he specialized in concepts of Artificial intelligence with Deep Learning algorithms. At the time, he was a part of the Machine Learning lab and has published technical papers, supported research into different avenues of AI. He published research on Cross-Modal Fusion with Transformer architecture for Sign Language translation during the completion of his Masters. He has also worked at Oracle, where he build and integrated Machine Learning solutions to provide operational benefits of using Oracle Clinical Trial software.

Author:

David Tai

Senior Staff Engineer
DiDi Autonomous Driving
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David Tai

Senior Staff Engineer
DiDi Autonomous Driving

The relentless growth in the size and sophistication of AI models and data sets continues to put pressure on every aspect of AI processing systems. Advances in domain-specific architectures and hardware/software co-design have resulted in enormous increases in AI processing performance, but the industry needs even more. Memory systems and interconnects that supply data to AI processors will continue to be of critical importance, requiring additional innovation to meet the needs of future processors. Join Rambus Fellow and Distinguished Inventor, Dr. Steven Woo, as he leads a panel of technology experts in discussing the importance of improving memory and interfaces and enabling new system architectures, in the quest for greater AI/ML performance.

Chip Design
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Hardware Engineering
Strategy
Systems Engineering

Author:

Steven Woo

Fellow and Distinguished Inventor
Rambus

I was drawn to Rambus to focus on cutting edge computing technologies. Throughout my 15+ year career, I’ve helped invent, create and develop means of driving and extending performance in both hardware and software solutions. At Rambus, we are solving challenges that are completely new to the industry and occur as a response to deployments that are highly sophisticated and advanced.

As an inventor, I find myself approaching a challenge like a room filled with 100,000 pieces of a puzzle where it is my job to figure out how they all go together – without knowing what it is supposed to look like in the end. For me, the job of finishing the puzzle is as enjoyable as the actual process of coming up with a new, innovative solution.

For example, RDRAM®, our first mainstream memory architecture, implemented in hundreds of millions of consumer, computing and networking products from leading electronics companies including Cisco, Dell, Hitachi, HP, Intel, etc. We did a lot of novel things that required inventiveness – we pushed the envelope and created state of the art performance without making actual changes to the infrastructure.

I’m excited about the new opportunities as computing is becoming more and more pervasive in our everyday lives. With a world full of data, my job and my fellow inventors’ job will be to stay curious, maintain an inquisitive approach and create solutions that are technologically superior and that seamlessly intertwine with our daily lives.

After an inspiring work day at Rambus, I enjoy spending time with my family, being outdoors, swimming, and reading.

Education

  • Ph.D., Electrical Engineering, Stanford University
  • M.S. Electrical Engineering, Stanford University
  • Master of Engineering, Harvey Mudd College
  • B.S. Engineering, Harvey Mudd College

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Steven Woo

Fellow and Distinguished Inventor
Rambus

I was drawn to Rambus to focus on cutting edge computing technologies. Throughout my 15+ year career, I’ve helped invent, create and develop means of driving and extending performance in both hardware and software solutions. At Rambus, we are solving challenges that are completely new to the industry and occur as a response to deployments that are highly sophisticated and advanced.

As an inventor, I find myself approaching a challenge like a room filled with 100,000 pieces of a puzzle where it is my job to figure out how they all go together – without knowing what it is supposed to look like in the end. For me, the job of finishing the puzzle is as enjoyable as the actual process of coming up with a new, innovative solution.

For example, RDRAM®, our first mainstream memory architecture, implemented in hundreds of millions of consumer, computing and networking products from leading electronics companies including Cisco, Dell, Hitachi, HP, Intel, etc. We did a lot of novel things that required inventiveness – we pushed the envelope and created state of the art performance without making actual changes to the infrastructure.

I’m excited about the new opportunities as computing is becoming more and more pervasive in our everyday lives. With a world full of data, my job and my fellow inventors’ job will be to stay curious, maintain an inquisitive approach and create solutions that are technologically superior and that seamlessly intertwine with our daily lives.

After an inspiring work day at Rambus, I enjoy spending time with my family, being outdoors, swimming, and reading.

Education

  • Ph.D., Electrical Engineering, Stanford University
  • M.S. Electrical Engineering, Stanford University
  • Master of Engineering, Harvey Mudd College
  • B.S. Engineering, Harvey Mudd College

Author:

Euicheol Lim

Research Fellow, System Architect
SK Hynix

Eui-cheol Lim is a Research Fellow and leader of Solution Advanced Technology team in SK Hynix. He received the B.S. degree and the M.S. degree from Yonsei University, Seoul, Korea, in 1993 and 1995, and the Ph.D. degree from Sungkyunkwan University, suwon, Korea in 2006. Dr.Lim joined SK Hynix in 2016 as a system architect in memory system R&D. Before joining SK Hynix, he had been working as an SoC architect in Samsung Electronics and leading the architecture of most Exynos mobile SoC. His recent interesting points are memory and storage system architecture with new media memory and new memory solution such as CXL memory and Processing in Memory. In particular, he is proposing a new computing architecture based on PIM, which is more efficient and flexible than existing AI accelerators, to process generative AI and LLM (large language Model) that is currently causing a sensation.

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Euicheol Lim

Research Fellow, System Architect
SK Hynix

Eui-cheol Lim is a Research Fellow and leader of Solution Advanced Technology team in SK Hynix. He received the B.S. degree and the M.S. degree from Yonsei University, Seoul, Korea, in 1993 and 1995, and the Ph.D. degree from Sungkyunkwan University, suwon, Korea in 2006. Dr.Lim joined SK Hynix in 2016 as a system architect in memory system R&D. Before joining SK Hynix, he had been working as an SoC architect in Samsung Electronics and leading the architecture of most Exynos mobile SoC. His recent interesting points are memory and storage system architecture with new media memory and new memory solution such as CXL memory and Processing in Memory. In particular, he is proposing a new computing architecture based on PIM, which is more efficient and flexible than existing AI accelerators, to process generative AI and LLM (large language Model) that is currently causing a sensation.

Author:

Sumti Jairath

Chief Architect
SambaNova Systems

Sumti Jairath is Chief Architect at SambaNova Systems, with expertise in hardware-software co-design. Sumti worked on PA-RISC-based Superdome servers back at HP, followed by several generations of SPARC CMT processors at Sun Microsystems and Oracle. At Oracle, Sumti worked on SQL, Data-analytics and Machine Learning acceleration in SPARC processors. Sumti holds 27 patents in computer architecture and hardware-software co-design.

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Sumti Jairath

Chief Architect
SambaNova Systems

Sumti Jairath is Chief Architect at SambaNova Systems, with expertise in hardware-software co-design. Sumti worked on PA-RISC-based Superdome servers back at HP, followed by several generations of SPARC CMT processors at Sun Microsystems and Oracle. At Oracle, Sumti worked on SQL, Data-analytics and Machine Learning acceleration in SPARC processors. Sumti holds 27 patents in computer architecture and hardware-software co-design.

Author:

Matt Fyles

SVP, Software
Graphcore

Matt Fyles is a computer scientist with over 20 years of proven experience in the design, delivery and the support of software and hardware within the microprocessor market. As SVP Software at Graphcore, Matt has built the company’s Poplar software stack from scratch, co-designed with the IPU for machine intelligence. He currently oversees the Software team’s work on the Poplar SDK, helping to support Graphcore’s growing community of developers.

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Matt Fyles

SVP, Software
Graphcore

Matt Fyles is a computer scientist with over 20 years of proven experience in the design, delivery and the support of software and hardware within the microprocessor market. As SVP Software at Graphcore, Matt has built the company’s Poplar software stack from scratch, co-designed with the IPU for machine intelligence. He currently oversees the Software team’s work on the Poplar SDK, helping to support Graphcore’s growing community of developers.

Enterprise AI
ML at Scale
Data Science
Software Engineering
Strategy

Author:

Dr. Caiming Xiong

VP of AI Research and Applied AI
Salesforce

Dr. Caiming Xiong is VP of AI Research and Applied AI at Salesforce. Dr. Xiong holds a Ph.D. from the department of Computer Science and Engineering, University at Buffalo, SUNY and worked as a Postdoctoral Researcher Scholar at the University of California, Los Angeles (UCLA).

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Dr. Caiming Xiong

VP of AI Research and Applied AI
Salesforce

Dr. Caiming Xiong is VP of AI Research and Applied AI at Salesforce. Dr. Xiong holds a Ph.D. from the department of Computer Science and Engineering, University at Buffalo, SUNY and worked as a Postdoctoral Researcher Scholar at the University of California, Los Angeles (UCLA).

We have witnessed a big paradigm shift in how AI has affected our daily lives. While AI model training is typically done in a cloud infrastructure setting, model inferencing has grown enormously on power, area, bandwidth and memory constrained edge devices.

These inferencing workloads have varying computational and memory needs, stringent power and silicon area requirements that can be very challenging to meet. AI led innovation is affecting the next generation of embedded hardware and software design alike. This talk will illustrate the design philosophies and challenges around designing best in class AI hardware accelerators.

 

Chip Design
Novel AI Hardware
Hardware Engineering
Strategy
Systems Engineering

Author:

Sriraman Chari

Fellow & Head of AI Accelerator IP Solution
Cadence Design Systems
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Sriraman Chari

Fellow & Head of AI Accelerator IP Solution
Cadence Design Systems

In developing applications for a variety of different infrastructure and hardware targets, machine learning developers face a dynamic and uncertain landscape where optimization and interoperability become challenging tasks. 

This panel will address how to build infrastructure with developer efficiency in mind, so that developers can focus on creating game-changing machine learning solutions for organizations and consumers. It will also address how hardware, systems and other technology vendors can assist in this effort.

Developer Efficiency
Enterprise AI
ML at Scale
Systems Design
Data Science
Software Engineering
Strategy
Systems Engineering

Author:

Ritu Goel

Director, Product Management, Adobe Sensei
Adobe

Ritu Goel is Director of Product Management at Adobe, where she has been driving strategy for AI/ML platform since its early days with the vision of democratizing AI/ML development at Adobe. Prior to this, Ritu has spent more than a decade leading product strategy and execution of various enterprise to consumer products and platforms at eBay, Macys.com and Infosys. Ritu has a bachelor of engineering from Indian Institute of Technology, Roorkee. 

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Ritu Goel

Director, Product Management, Adobe Sensei
Adobe

Ritu Goel is Director of Product Management at Adobe, where she has been driving strategy for AI/ML platform since its early days with the vision of democratizing AI/ML development at Adobe. Prior to this, Ritu has spent more than a decade leading product strategy and execution of various enterprise to consumer products and platforms at eBay, Macys.com and Infosys. Ritu has a bachelor of engineering from Indian Institute of Technology, Roorkee. 

Author:

Jeff Boudier

Product Director
Hugging Face

Jeff Boudier is a product director at Hugging Face, creator of Transformers, the leading open-source NLP library. Previously Jeff was a co-founder of Stupeflix, acquired by GoPro, where he served as director of Product Management, Product Marketing, Business Development and Corporate Development.

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Jeff Boudier

Product Director
Hugging Face

Jeff Boudier is a product director at Hugging Face, creator of Transformers, the leading open-source NLP library. Previously Jeff was a co-founder of Stupeflix, acquired by GoPro, where he served as director of Product Management, Product Marketing, Business Development and Corporate Development.

Author:

Sree Ganesan

VP of Product
d-Matrix

Sree Ganesan, VP of Product, d-Matrix: Sree is responsible for product management functions and business development efforts across the company. She manages the product lifecycle, definition and translation of customer needs to the product development function, acting as the voice of the customer. Prior, Sree led the Software Product Management effort at Habana Labs/Intel, delivering state-of-the-art deep learning capabilities of the Habana SynapseAI® software suite to the market. Previously, she was Engineering Director in Intel’s AI Products Group, where she was responsible for AI software strategy and deep learning framework integration for Nervana NNP AI accelerators. Sree earned a bachelor’s degree in electrical engineering from the Indian Institute of Technology Madras and a PhD in computer engineering from the University of Cincinnati, Ohio.

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Sree Ganesan

VP of Product
d-Matrix

Sree Ganesan, VP of Product, d-Matrix: Sree is responsible for product management functions and business development efforts across the company. She manages the product lifecycle, definition and translation of customer needs to the product development function, acting as the voice of the customer. Prior, Sree led the Software Product Management effort at Habana Labs/Intel, delivering state-of-the-art deep learning capabilities of the Habana SynapseAI® software suite to the market. Previously, she was Engineering Director in Intel’s AI Products Group, where she was responsible for AI software strategy and deep learning framework integration for Nervana NNP AI accelerators. Sree earned a bachelor’s degree in electrical engineering from the Indian Institute of Technology Madras and a PhD in computer engineering from the University of Cincinnati, Ohio.

Author:

Daniel Wu

Strategic AI Leadership | Keynote Speaker | Educator | Entrepreneur Course Facilitator
Stanford University

Daniel Wu is an accomplished technical leader with over 20 years of expertise in software engineering, AI/ML, and team development. With a diverse career spanning technology, education, finance, and healthcare, he is credited for establishing high-performing AI teams, pioneering point-of-care expert systems, co-founding a successful online personal finance marketplace, and leading the development of an innovative online real estate brokerage platform. Passionate about technology democratization and ethical AI practices, Daniel actively promotes these principles through involvement in computer science and AI/ML education programs. A sought-after speaker, he shares insights and experiences at international conferences and corporate events. Daniel holds a computer science degree from Stanford University.

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Daniel Wu

Strategic AI Leadership | Keynote Speaker | Educator | Entrepreneur Course Facilitator
Stanford University

Daniel Wu is an accomplished technical leader with over 20 years of expertise in software engineering, AI/ML, and team development. With a diverse career spanning technology, education, finance, and healthcare, he is credited for establishing high-performing AI teams, pioneering point-of-care expert systems, co-founding a successful online personal finance marketplace, and leading the development of an innovative online real estate brokerage platform. Passionate about technology democratization and ethical AI practices, Daniel actively promotes these principles through involvement in computer science and AI/ML education programs. A sought-after speaker, he shares insights and experiences at international conferences and corporate events. Daniel holds a computer science degree from Stanford University.

 

Edge AI
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Software Engineering
Strategy
Systems Engineering
Hardware Engineering

Author:

Victor Peng

President, Adaptive and Embedded Computing Group
AMD

Victor Peng is President of the Adaptive and Embedded Computing group at AMD. He is responsible for AMD’s Adaptive SmartNIC, FPGA, Adaptive SoC, embedded CPU, and embedded APU business that serve multiple market segments including the data center, communications, automotive, industrial, A&D, healthcare, test/measure/emulation, and other embedded markets. Peng also serves on the board of KLA Corporation.

Peng rejoined AMD in 2022 after 14 years at Xilinx, most recently serving as president and CEO. Prior to joining Xilinx, Peng worked at AMD as corporate vice president of silicon engineering for the graphics products group (GPG) and was the co-leader of the central silicon engineering team supporting graphics, game console products, and CPU chipsets. Prior to that, Peng held executive and engineering leadership roles at ATI, TZero Technologies, MIPS Technologies, SGI, and Digital Equipment Corp. 

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Victor Peng

President, Adaptive and Embedded Computing Group
AMD

Victor Peng is President of the Adaptive and Embedded Computing group at AMD. He is responsible for AMD’s Adaptive SmartNIC, FPGA, Adaptive SoC, embedded CPU, and embedded APU business that serve multiple market segments including the data center, communications, automotive, industrial, A&D, healthcare, test/measure/emulation, and other embedded markets. Peng also serves on the board of KLA Corporation.

Peng rejoined AMD in 2022 after 14 years at Xilinx, most recently serving as president and CEO. Prior to joining Xilinx, Peng worked at AMD as corporate vice president of silicon engineering for the graphics products group (GPG) and was the co-leader of the central silicon engineering team supporting graphics, game console products, and CPU chipsets. Prior to that, Peng held executive and engineering leadership roles at ATI, TZero Technologies, MIPS Technologies, SGI, and Digital Equipment Corp. 

 

Developer Efficiency
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Software Engineering
Strategy
Systems Engineering

Author:

Mark Russinovich

CTO and Technical Fellow, Azure
Microsoft

Mark Russinovich is Chief Technology Officer and Technical Fellow for Microsoft Azure, Microsoft’s global enterprise-grade cloud platform. A widely recognized expert in distributed systems, operating systems and cybersecurity, Mark earned a Ph.D. in computer engineering from Carnegie Mellon University. He later co-founded Winternals Software, joining Microsoft in 2006 when the company was acquired. Mark is a popular speaker at industry conferences such as Microsoft Ignite, Microsoft Build, and RSA Conference. He has authored several nonfiction and fiction books, including the Microsoft Press Windows Internals book series, Troubleshooting with the Sysinternals Tools, as well as fictional cyber security thrillers Zero Day, Trojan Horse and Rogue Code.

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Mark Russinovich

CTO and Technical Fellow, Azure
Microsoft

Mark Russinovich is Chief Technology Officer and Technical Fellow for Microsoft Azure, Microsoft’s global enterprise-grade cloud platform. A widely recognized expert in distributed systems, operating systems and cybersecurity, Mark earned a Ph.D. in computer engineering from Carnegie Mellon University. He later co-founded Winternals Software, joining Microsoft in 2006 when the company was acquired. Mark is a popular speaker at industry conferences such as Microsoft Ignite, Microsoft Build, and RSA Conference. He has authored several nonfiction and fiction books, including the Microsoft Press Windows Internals book series, Troubleshooting with the Sysinternals Tools, as well as fictional cyber security thrillers Zero Day, Trojan Horse and Rogue Code.

Chip Design
Edge AI
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Software Engineering
Strategy
Systems Engineering

Author:

Rashid Attar

Head of Engineering, Cloud/Edge AI Inference Accelerators
Qualcomm

Rashid Attar joined Qualcomm, San Deigo, CA, USA, and has involved in various aspects CDMA wireless data (EV-DO) and voice systems (IS-95, 1x-Advanced) in 1996, where he was the Project Engineer of CDMA2000-advanced from 2009 to 2013 and CDMA Modem Systems Lead at QCT from 20 through 2013. From 2014 to mid-2016, he led the ultra-low-power ASIC platform project. He is currently a Vice President Engineering with Corporate Research and Development, Qualcomm. He leads the ASIC and Hardware Department in Qualcomm Research. The Qualcomm Research portfolio consists of Communications (5G, Cellular V2X, Satellite Communications, Wi-Fi, and Industrial Internet of Things), ASIC and HW Research and Development, and Embedded IoE systems (Always on computer vision, Autonomous Driving, Robotics, and AR/VR). The ASIC and Hardware Group Research and Development portfolio consists of 5G (RFICs, PAs, Interfaces, Packaging), processors (CPUs, Programmable deep learning accelerators), ultra-low-power platform (processor, communications, memory, machine learning accelerators, power management, wireless charging), core CMOS Research and Development (3-DIC and Thermal-aware designs), and Antenna Design. He holds approximately 160 granted U.S. patents

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Rashid Attar

Head of Engineering, Cloud/Edge AI Inference Accelerators
Qualcomm

Rashid Attar joined Qualcomm, San Deigo, CA, USA, and has involved in various aspects CDMA wireless data (EV-DO) and voice systems (IS-95, 1x-Advanced) in 1996, where he was the Project Engineer of CDMA2000-advanced from 2009 to 2013 and CDMA Modem Systems Lead at QCT from 20 through 2013. From 2014 to mid-2016, he led the ultra-low-power ASIC platform project. He is currently a Vice President Engineering with Corporate Research and Development, Qualcomm. He leads the ASIC and Hardware Department in Qualcomm Research. The Qualcomm Research portfolio consists of Communications (5G, Cellular V2X, Satellite Communications, Wi-Fi, and Industrial Internet of Things), ASIC and HW Research and Development, and Embedded IoE systems (Always on computer vision, Autonomous Driving, Robotics, and AR/VR). The ASIC and Hardware Group Research and Development portfolio consists of 5G (RFICs, PAs, Interfaces, Packaging), processors (CPUs, Programmable deep learning accelerators), ultra-low-power platform (processor, communications, memory, machine learning accelerators, power management, wireless charging), core CMOS Research and Development (3-DIC and Thermal-aware designs), and Antenna Design. He holds approximately 160 granted U.S. patents